The packaging and test stage takes wafers that meet quality standards through precision dicing, wire bonding and moulding to achieve electrical connection between the internal circuit and external devices, provide the necessary mechanical and physical protection, and use test tools to carry out comprehensive and rigorous functional and performance checks on the packaged chip. Obtaining an IC involves a complex flow from design to manufacturing. Because chips are so small and thin, they are easily scratched and damaged without adequate protection.

Packaging and test houses the chip, fixes it in place, seals and protects it and improves its thermal performance, and also acts as the bridge between the internal world of the chip and external circuits: the pads on the chip are connected by wire to the pins of the package, and those pins in turn connect to other devices through traces on the printed circuit board. Packaging and test therefore plays a vital role in integrated circuits.

From die to finished chip

The packaging and test flow is described below.

Wafer test

Before further processing, integrated circuit wafers must pass a strict test stage to confirm the functional integrity of each die. Testing classifies dies into three groups: good die with intact function, defective die with flaws, and fail die with no function at all. According to the product shipping classification requirements, dies that meet the requirements are selected for the next packaging production step. This process is called CP test, short for chip probing test, in which probes contact the die pads to verify normal function. This step is essential to ensuring final product quality.

CP test relies mainly on ATE (automatic test equipment, which supplies the power, signals and functional vectors needed for testing and receives the chip output feedback to judge the result), the prober (a high precision machine platform that carries and moves the wafer so that the probe card probes can contact and conduct to the die pads accurately) and the probe card (a test board customised to the circuit and test requirements of each chip, connecting the ATE channel resources to the corresponding die pads). Working together, these devices and components progressively test every die on the wafer. Problem dies are usually marked on the surface by inking so that they can be identified and picked out during subsequent packaging.

Running CP test on the wafer and packaging only functional dies effectively avoids the cost loss of packaging defective chips. A blind assembly strategy is sometimes used, packaging every die on the wafer without CP test and then testing and screening at a later stage. This is usually limited to initial engineering lots after tape-out, in order to obtain engineering samples as quickly as possible and verify whether the tape-out succeeded, saving project time. For volume production, CP test is indispensable.

The packaging process differs markedly depending on the final package type. Taking the common wire bond ball grid array package (WB-BGA) as an example, its production covers the main process steps of chip packaging.

Wafer dicing is an extremely fine and demanding process that separates the wafer that has passed CP test into individual dies. First the wafer is inspected to confirm it meets the dicing requirements. A protective blue tape is then applied to the front of the wafer to prevent damage during dicing. Depending on package dimensions and heat dissipation needs, the wafer may also be thinned by mechanical grinding. A diamond blade or laser then cuts precisely along the scribe lines predefined on the wafer, areas reserved during wafer manufacturing to protect the dies during cutting. Individual dies are obtained at the end of this step. Dicing demands very high precision, and any small process error can directly affect die quality, so the process depends on specialised production equipment, the wafer dicing saw. Well known dicing saw makers worldwide include DISCO and ACCRETECH of Japan and Slicingtech of the United States. In China, JingSheng Electromechanical and the 45th Research Institute of CETC have also made notable progress in this field.

The package substrate (SUB) plays a vital role in making the final chip. It is a special printed circuit board whose key function is to fan the die pads out to the package ball pins, so it must be designed and manufactured according to each chip and its package dimensions. Well known SUB makers include Kyocera of Japan and Nan Ya, Unimicron and Kinsus of Taiwan, China. On the mainland, Xingsen Technology, Zhuhai Access, Shennan Circuits and Shengyi Electronics are working to break through the SUB production technology needed for high end chip packaging.

Substrate chip side and ball side

The substrate forms the base structure of the package, much like the foundation of a building. The die is then placed precisely on one side of the substrate, a step called die attach. Die and substrate are connected by fine wire bonding. To ensure stability and safety a metal lid, usually made of an alloy with excellent heat dissipation, is mounted on top in a step called lid attach. On the other side, solder balls are mounted on the chip in a step called solder ball mount, and reflow then forms a solid connection between the balls and the substrate. The basic package structure is now complete.

After packaging the chip undergoes strict quality inspection, including X-ray and other techniques to examine the internal structure in detail and confirm package quality. Marking then prints the chip maker's logo, product name and production lot on the surface by laser. Once all quality indicators pass, the chip goes through baking to remove moisture and other factors in the packaging materials that could affect performance, ensuring stable and reliable electrical behaviour in later use.

Through this series of fine packaging processes the original wafer die finally becomes a finished chip, providing a solid foundation for subsequent applications.

Package structure

Beyond conventional wire bond BGA packaging, the mainstream approach today is flip chip BGA, which achieves a smaller package by mounting the chip face down and connecting it to the substrate. This technology first forms metal bumps on the wafer die pads by wafer bumping, and the bumps then connect to the substrate below. The differences from the earlier approach are clear. There are many package types; by material they fall mainly into plastic, ceramic and metal packages, with ceramic and metal used mainly in aerospace and military fields where operating conditions are extremely harsh and cost is relatively high. By structure the variety is even greater, since different chip types and application requirements call for different package structures.

Package structures by type

As demand for high performance chips rises and applications expand, packaging technology is evolving rapidly, moving from planar 2D packaging to 2.5D and 3D in order to keep raising integration density. Today's prominent AI SoCs must integrate and package two to eight or more high bandwidth HBM memory dies, known as KGD or known good die, which places higher demands on packaging technology. The advanced CoWoS 2.5D package was developed to ensure high speed, stable interconnect bandwidth between HBM memory stacks and the main die.

2.5D and 3D packaging

Final test

Before a chip is shipped to the end product customer, it must pass a critical test stage, final test, to confirm function and quality. This is necessary for two reasons. First, although CP test effectively assesses chip performance, probing at wafer level limits the power and frequency that can be applied. Second, packaging may cause some degree of damage through process factors. Final testing of the packaged product is therefore essential, since it effectively identifies and screens out latent quality problems.

FT uses methods similar to CP test and likewise relies on ATE. It also needs a load board and a handler. Together these ensure accurate and efficient final test and provide solid quality assurance for final shipment.

Final test process, related equipment and test hardware

System level test

As chip size, function and packaging technology advance, complexity grows, which significantly raises the cost of CP and FT and limits achievable test coverage. In fields with extremely strict defect rate requirements, such as autonomous driving chips, test quality requirements are even more demanding. To reduce the shipped defect rate, or DPPM, many chips add a system level test (SLT) stage after FT.

SLT is designed around the actual application scenario of the chip. Carefully built test boards and test flows simulate the real business workload of the chip during testing. This ensures that, before the chip is shipped to the customer and used on a real product board, it has passed a strict check much closer to the actual application scenario, driving DPPM even lower. This improves chip quality and strengthens customer confidence in the product.

Packaging and test are closely linked, which is why the industry often refers to typical suppliers as packaging and test houses. Shenzhen Zhongke System Integration Technology was founded in 2011 and has worked in advanced packaging for more than ten years, accumulating extensive experience in advanced packaging design simulation and process development. Its main business covers wafer level packaging, IC test board design and fabrication, hardware design and development, and one-stop advanced packaging solutions. Acquired in 2021 by Xinrui Micro (Shanghai) Electronic Technology, it is now a leading domestic one-stop advanced system in package design service provider, with products widely used in aerospace, automotive, marine, communications, electronics and medical industries.

Chip packaging and test is an important stage of the semiconductor industry chain and is vital to the physical protection, functional integrity and performance reliability of integrated circuits. As technology advances, packaging and test will continue to move toward miniaturisation, high density and high integration, for example through 3D packaging and wafer level packaging. These innovations allow chips to deliver more diverse functions and better performance in a more compact space, meeting the growing needs of applications such as artificial intelligence, the Internet of Things, 5G communications and automotive electronics. This not only drives the semiconductor industry but also injects new vitality and opportunity into the wider technology sector.

About NTEK

NTEK Group was founded in 2009 and is headquartered in Shenzhen. The group provides quality research and technical services covering R&D verification, inspection and testing, failure analysis, simulation and market access for intelligent connected vehicles, electronic communications and new energy.

NTEK has extensive experience in automotive-grade electronic certification and has helped more than 100 companies pass AEC-Q series certification. Driven by the need of vehicle makers to localise automotive-grade components and supported by the domestic semiconductor industry, NTEK provides comprehensive testing and certification services, applying AEC-Q automotive standards to control the safety and quality of automotive components, supporting the growth of domestic automotive-grade components and adding new momentum to the intelligent vehicle safety system.