1. Autonomous driving compute chips

1.1 Introduction

An autonomous driving chip is a SoC that can enable high level autonomous driving. As a general purpose processor, the CPU suits complex calculations in moderate quantity. Beyond meeting compute requirements, it can handle complex conditions and branches and the synchronisation and coordination between tasks.

Chip performance is generally assessed by the three PPA indicators: power, performance and area. In intelligent driving, peak compute has become the main indicator for autonomous driving chips. At the 2020 Global Artificial Intelligence and Robotics Summit, Horizon proposed MAPS (Mean Accuracy-guaranteed Processing Speed) as a way to evaluate chip AI performance. Horizon argues that real AI efficiency has three elements: theoretical peak compute efficiency, effective utilisation and AI algorithm efficiency. First, theoretical peak compute efficiency covers TOPS/W and TOPS per dollar, the conventional peak metric. Second, effective utilisation is obtained by deploying an algorithm on the chip and using compilers and other systematic methods to solve an extremely complex discrete optimisation problem with constraints according to the architecture, giving the actual utilisation of an algorithm on the chip; this is the optimisation target of software and hardware compute architecture. Third, AI algorithm efficiency describes how much actual AI algorithm performance each TOPS of compute delivers, reflecting continuous improvement in AI algorithm efficiency.

1.2 Development trends

In core compute scenarios such as autonomous driving, traditional general purpose CPUs have low computational efficiency and struggle to meet AI requirements. AI chips such as GPU, FPGA and ASIC perform well at the edge and in the cloud thanks to their characteristics and are more widely used. Technically, GPUs will continue to dominate AI chips in the near term, while ASICs are the ultimate direction in the long term. From a market perspective, global AI chip demand will maintain rapid growth, with significant potential in both cloud and edge chips and market growth of close to 50 percent expected over the next five years. Although domestic chip technology has a weaker foundation, rapid deployment of AI applications is driving rapid growth in AI chip demand, creating opportunities for domestic companies to develop their technology and capability. Autonomous driving has strict requirements for compute, latency and reliability, and GPU plus FPGA solutions are currently common; as algorithms stabilise and become data driven, ASICs are expected to gain market space.

A CPU needs considerable space for branch prediction and optimisation and for storing state to reduce task switching latency, which makes it better suited to logic control, serial computation and general purpose data processing. Comparing GPU with CPU: a GPU uses a large number of compute units and very long pipelines, with only very simple control logic and no cache. A CPU not only devotes much of its area to cache but also has complex control logic and many optimisation circuits, so compute is only a small part of it.

As autonomous vehicles become more intelligent, the volume of data to be processed grows, and high definition maps, sensors and lidar place higher demands on compute. Adding acceleration chips with AI capability alongside the CPU as general purpose processor has therefore become mainstream.

Common AI acceleration chips fall into three types: GPU, ASIC and FPGA.

(1) GPU: suited to very large numbers of relatively simple operations. A GPU has a massively parallel architecture made of thousands of smaller, more efficient ALU cores, with most transistors used for control circuits and cache. Control circuits are relatively simple, and the GPU has stronger floating point processing capability and is better at handling multiple tasks such as graphics computation.

(2) FPGA: field programmable gate array, developed from programmable devices such as PAL, GAL and CPLD. It emerged as a semi-custom circuit in the ASIC field, solving the shortcomings of custom circuits while overcoming the limited number of gate circuits in earlier programmable devices.

(3) ASIC: an integrated circuit designed for a specific purpose, designed and manufactured to meet the requirements of a specific customer and electronic system. ASICs target specific customer needs and, in volume production, offer smaller size, lower power, higher reliability, higher performance, stronger confidentiality and lower cost than general purpose integrated circuits.

CPU plus XPU is the mainstream trend in current autonomous driving SoC design. Depending on the XPU chosen, there are three technical routes: CPU plus GPU plus ASIC, CPU plus ASIC, and CPU plus FPGA.

(1) CPU plus GPU plus ASIC, represented mainly by Nvidia, Tesla FSD and Qualcomm Ride. Nvidia Xavier and Tesla FSD adopt this route. Nvidia Xavier uses the GPU as its compute core and has four main blocks: CPU, GPU, and two ASIC chips, the deep learning accelerator (DLA) and the programmable vision accelerator (PVA). The Tesla FSD chip uses an NPU, an ASIC, as its compute core and has three main blocks.

(2) CPU plus ASIC, represented mainly by Mobileye EyeQ5 and the Horizon Journey series. EyeQ5 has four main blocks: CPU, computer vision processors (CVP), deep learning accelerator (DLA) and multithreaded accelerator (MA), where CVP is an ASIC designed for conventional computer vision algorithms. Horizon has independently designed the brain processing unit (BPU), an AI specific ASIC, alongside CPU, GPU and neural processing unit (NPU).

(3) CPU plus FPGA, represented mainly by Waymo. Unlike other companies, Waymo uses a CPU plus FPGA architecture, with a compute platform built on Intel Xeon CPUs of 12 cores or more paired with Altera Arria series FPGAs.

1.3 Industry landscape

Most of the latest chip platforms can support the compute needs of L3 or L4 driving, with Nvidia relatively ahead and domestic suppliers still some way behind. A single Nvidia Orin delivers 254 TOPS, while the NIO ET7 and WM M7, launched in 2022 with four Orin chips each, reach peak compute of more than 1000 TOPS. The Qualcomm Snapdragon Ride platform is expected to deliver 700 to 760 TOPS peak, and Mobileye has launched EyeQ6 Ultra for high level autonomous driving with 176 TOPS.

China's automotive compute chips are still at a relatively early stage. In compute platforms, domestic leaders have developed their own CPU, GPU, FPGA and ASIC products and match international suppliers on most technical indicators, and some central control and high compute chips already have successful automotive application experience. Across the industry, however, domestic automotive compute chips still lag in product reliability and automotive application experience, leaving substantial room for import substitution.

In the long run, domestic compute chip suppliers are expected to meet most of the needs of domestic vehicle makers. Self-owned brand vehicle makers are accelerating multi-supplier strategies for core chips and actively advancing testing and nomination of domestic suppliers, while domestic automotive AI companies, consumer chip makers and automotive chip startups are investing in development and gradually achieving in-vehicle application.

2. Smart cockpit compute chips

2.1 Introduction

A cockpit domain controller meets the requirements of lightweight construction and intelligence in a centralised form, supporting the rich functions and strong interactivity of the vehicle cockpit. In hardware terms, a cockpit domain controller consists of a main cockpit compute SoC and peripheral circuits including memory chips such as LPDDR and NOR flash, communication chips such as Ethernet switch chips, audio and video data interfaces and related processing chips such as ISP, DSP and deserialiser. Enabled by the operating system and application ecosystem, the cockpit domain controller integrates instrument display, infotainment, navigation, HUD and driver and occupant monitoring, connects peripherals including displays, cameras, microphones and radio, and is the direct carrier of the technological feel of the cockpit space.

The cockpit compute SoC is the core of the smart cockpit and consists of processor, memory, system control, encryption algorithms and communication interfaces.

(1) Processor. The core of the cockpit SoC usually includes heterogeneous processors such as CPU, GPU, VPU and NPU. First, the CPU is the central processing unit, and its core count and clock frequency largely determine information processing performance. Chips of different grades in the same series are usually differentiated by the number of CPU cores: the NXP i.MX 8 Quad, QuadPlus and QuadMax, for example, differ mainly by carrying zero, one or two Arm Cortex A72 cores. Second, the GPU and VPU are processors dedicated to processing and rendering image and video information, relieving pressure on the CPU and providing a better audio and video experience. Third, the NPU uses a data driven parallel computing architecture and handles AI compute requirements.

(2) Memory. On-chip memory stores both unprocessed and processed data to improve data processing efficiency, and includes DRAM, SD, eMMC and NAND together with data transmission interfaces such as QSPI and SPI.

(3) Security and system control. The former covers various encryption algorithms, the latter control systems such as power management and clocks.

(4) Communication interfaces. These include general purpose internal data interfaces such as PCIe, LVDS, USB, SATA, CAN and Ethernet, and interfaces for video input and output to cockpit displays and cameras such as DSI, CSI, HDMI, eDP and DP.

Cockpit chip compute determines the data capacity, data processing speed and image rendering capability of the cockpit domain controller, and therefore the number of displays, operating smoothness and picture richness in the cockpit, shaping the intelligent experience of the whole cockpit space. Although domain controllers are supplied by many domestic and international companies, the chip platforms they are based on are limited and largely concentrated among Qualcomm, Renesas, NXP and TI, so cockpit chips are notably more concentrated than domain controllers.

As intelligence deepens, so do requirements for cockpit chip compute. IHS estimates that in 2024 smart cockpits will require 89k DMIPS of CPU compute, more than three times the 2021 requirement. Compute differs markedly between the main cockpit chip suppliers: the latest platforms from Qualcomm and Samsung deliver 80 to 150k DMIPS, while conventional automotive chip makers Renesas, NXP and Texas Instruments deliver roughly 25 to 50k DMIPS.

2.2 Development trends

As vehicle E/E architectures evolve from distributed to domain centralised to central computing, cockpit chip solutions will also evolve through three stages: single chip single screen, single chip multiple screens, and converged development.

(1) Single chip single screen: disadvantages in signal transmission and cost. Under a distributed architecture, each cockpit electronic device is controlled by a separate controller, giving single chip single screen. This was appropriate when cockpit functions were limited: screens did not need to exchange information, chip performance requirements were modest and cost was controllable, and because the instrument cluster and infotainment screen ran different systems, the solution was easy to implement.

As consumers emphasise the in-vehicle experience, LCD clusters replace mechanical clusters, infotainment screens carry more data and data exchange between devices becomes more frequent, so single chip single screen struggles to meet market demand. First, cross-chip signal transmission introduces latency. In the intelligent era cockpit electronics exchange information frequently; driving information in the cluster, for example, interacts with central control navigation. Multi-screen interaction requires high speed transmission between devices, but in single chip single screen different chips communicate over CAN or LIN buses, where signal rate hits a bottleneck. Second, cost pressure rises. To convey a sense of technology, cluster information richness and infotainment screen smoothness increase substantially, placing higher demands on a single chip and inevitably raising its price. New devices such as HUD and streaming mirrors also raise the per-vehicle cost of cockpit electronics.

(2) Single chip multiple screens: the mainstream approach for centralised architectures. Single chip multiple screens means one cockpit SoC processes and controls the signals of several cockpit electronic devices. The Visteon SmartCore cockpit domain controller was the first to integrate different controllers, combining a fully digital cluster and central information display on a single chip to achieve single chip multiple screens, in line with the centralisation trend in vehicle E/E architectures.

Single chip multiple screens has become the mainstream solution to the signal latency and per-vehicle cost problems of single chip single screen. First, it addresses signal latency. According to Cerebras, on-chip data transmission can reach 100 PB/s, 100,000 times the fastest inter-chip interface. Single chip multiple screens turns inter-chip communication into on-chip communication, raising transmission rate. Second, on cost, the number of chips falls from several to one; although the value of that chip rises, overall cost is lower.

Integration does create another problem, however: cross-system operation. A digital LCD cluster is relevant to vehicle safety and must meet ASIL-B, so it usually runs QNX or Linux, while the infotainment system needs rich entertainment functions and usually runs Android. In single chip single screen these systems are supported by different chips, so there is no cross-system issue; in single chip multiple screens, cross-system operation reduces compute efficiency noticeably.

Hardware partitioning and virtualisation are expected to solve this. First, hardware partitioning allocates hardware resources between systems in advance, dividing the compute resources, memory and peripherals each system may access, and systems may not access each other's hardware resources. The NXP i.MX 8 QM, for example, uses hardware partitioning to divide the SoC into a cluster system running Linux and an infotainment system running Android. Second, a hypervisor inserts a layer between the operating system and the hardware, scheduling compute units and memory for each virtual machine and dynamically allocating hardware resources. The Visteon SmartCore mentioned above uses virtualisation.

(3) Cross-domain convergence: merging with autonomous driving chips. Under a central computing architecture, a central compute chip handles autonomous driving, the smart cockpit and whole vehicle control, acting as the hub for massive volumes of data measured in terabytes. This requires greater data throughput and faster processing; more data processing means more power and heat, which requires more refined hardware reference design; and the complex converged system of ADAS, cockpit and vehicle control requires stronger software development capability.

A central computing architecture requires more demanding software and hardware capability, which may be what constrains vehicle architectures from moving to a more centralised stage. Cockpit chips and autonomous driving chips are currently developing separately, but as hardware compute, architecture design and software development capability improve and vehicle architectures move to central computing, the two are expected to converge.

Bosch cockpit chip evolution roadmap

2.3 Competitive landscape

The overseas supplier landscape is becoming clearer, with two camps competing.

Overseas suppliers fall into two camps. The first comprises conventional automotive chip makers such as NXP, Renesas and Texas Instruments, which beyond their traditional automotive MCU and ECU business are positioning in cockpit chips as intelligence spreads. The second comprises consumer chip makers such as Qualcomm and Samsung, which have entered the automotive cockpit field and are reusing their deep consumer electronics technology accumulation.

Conventional automotive chip makers still hold a large share. According to Gaogong Intelligent Automobile Research Institute, NXP, Renesas and Texas Instruments are the main smart cockpit chip suppliers, largely because mid and low end models account for a large share of vehicle sales. Conventional automotive chip makers have been slower in the intelligence transition and, beyond meeting automotive safety requirements, do not match consumer chip makers on performance. The Renesas R-CAR H3 uses a 16 nm process, while the NXP i.MX 8 series and Texas Instruments Jacinto 7 are both designed on 28 nm with CPU compute of up to 40k DMIPS.

Consumer chips have a clear performance advantage, and Qualcomm almost monopolises the high end cockpit chip market. The latest cockpit chips from Qualcomm and Samsung already use a 5 nm process. The Qualcomm Snapdragon 8295 became the mainstream standard for smart cockpit chips in 2024: with a 5 nm process and major gains in CPU, GPU and AI performance, it delivers twice the CPU compute, two to three times the GPU and eight times the AI compute of the previous 8155, and is widely used in models including the Mercedes-Benz E-Class, Geely Galaxy E8, Xpeng X9, NIO ET9, Xiaomi SU7, Jiyue 01 and Leapmotor C10.

Consumer chip makers have natural advantages entering the cockpit field. On one hand, current smart cockpit compute requirements remain within the range of smartphones; Roland Berger expects that within five years high end phone chip compute will still support next generation cockpit electronics requirements. On the other hand, consumer chip makers already have scale advantages in phones and other consumer electronics and can develop at low cost. New entrants carry more sunk cost in fixed assets and research and development, and whether they reach break-even depends on nominated model cooperation and sales, so initial costs are high.

China's cockpit chips are at an early stage of development. In time, the domestic cockpit chip market is still early; in terms of participants, the market brings together automotive AI chip companies, consumer chip makers and automotive chip startups. Automotive AI companies such as Horizon and Black Sesame offer products that can support cockpit applications. Consumer chip makers such as Huawei and Allwinner are widely positioned in phones, computers, smart home and communications. A group of automotive chip startups has also entered, such as SemiDrive, founded in 2018 and releasing the X9 series in 2020 to support cockpit intelligence, and SiEngine, founded in 2018, which designed the 7 nm SE1000 and expected to begin in-vehicle testing in 2022.

The domestic cockpit chip competitive landscape is not yet settled. Apart from a few vehicle makers such as Xpeng that deal directly with cockpit chip suppliers, most shape cockpit intelligence by working with cockpit domain controller tier one suppliers. Several chips already have deployment scenarios: the Huawei Kirin 990A is used in the BAIC Arcfox Alpha S, and the Horizon Journey 2 has been deployed in models including the Changan UNI-K, while SiEngine is tied to Geely. According to SemiDrive, the company now serves more than 250 customers covering 70 percent of Chinese vehicle makers and has won more than 50 nominated projects.

After the automotive chip shortage of 2021, self-owned brand vehicle makers have adopted multi-supplier strategies for core chips and are actively advancing testing and nomination of domestic suppliers. As market application continues to expand, the gap between domestic cockpit SoCs and international giants will gradually narrow.

The table below summarises current mainstream smart cockpit SoCs.

Comparison of current mainstream smart cockpit SoC chips

3. AEC-Q100: the threshold for driving and cockpit compute chips

1. AEC-Q certification is the entry threshold for automotive electronics. AEC stands for Automotive Electronics Council. It was founded in 1994 by Chrysler, Ford and General Motors, and its membership now spans major vehicle makers, automotive electronics companies and semiconductor manufacturers worldwide. Components that comply with AEC specifications can be adopted by all three manufacturers at the same time, which encouraged part makers to exchange product characteristic data, drove standardisation of automotive parts and laid the foundation for the rapid growth of the automotive parts market. AEC-Q is the automotive reliability test standard issued by the AEC and an important passport for part makers entering automotive electronics and tier one supply chains.

AEC-Q100 was the first AEC standard, a set of stress test specifications designed for integrated circuits in automotive applications. It is important for improving product reliability and quality assurance. AEC-Q100 confirms the quality and reliability of each chip against possible conditions and latent failure states, with standardised tests of product function and performance in particular.

2. Automotive ICs required to pass AEC-Q100. Single chip ICs: control, driver, computing, memory, sensor, communication, power, power supply, security and analogue chips.

3. AEC-Q100 operating temperature grades for integrated circuits.

▸ Grade 0: ambient operating temperature -40℃ to 150℃
▸ Grade 1: ambient operating temperature -40℃ to 125℃
▸ Grade 2: ambient operating temperature -40℃ to 105℃
▸ Grade 3: ambient operating temperature -40℃ to 85℃

4. AEC-Q100 validation flow for automotive IC products.

5. AEC-Q100 test groups.

Group A, accelerated environmental stress tests (PC, THB/HAST, AC or UHAST or TH, TC, PTC, HTSL): 6 tests
Group B, accelerated lifecycle simulation (HTOL, ELFR, EDR): 3 tests
Group C, package assembly integrity (WBS, WBP, SD, PD, SBS, LI, BST): 7 tests
Group D, die fabrication reliability (EM, TDDB, HCI, BTI, SM): 5 tests
Group E, electrical verification (TEST, HBM, CDM, LU, ED, FG, CHAR, EMC, SC, SER, LF): 11 tests
Group F, defect screening (PAT, SBA): 2 tests
Group G, cavity package integrity (MS, VFV, CA, GFL, DROP, LT, DS, IWV): 8 tests

6. NTEK chip testing capability and AEC-Q100 requirements.

About NTEK

NTEK Group was founded in 2009 and is headquartered in Shenzhen. The group provides quality research and technical services covering R&D verification, inspection and testing, failure analysis, simulation and market access for intelligent connected vehicles, electronic communications and new energy.

NTEK has extensive experience in automotive-grade electronic certification and has helped more than 100 companies pass AEC-Q series certification, confirming the quality and reliability of each chip case against AEC-Q100.

Driven by the need of vehicle makers to localise automotive-grade chips and supported by the domestic semiconductor industry, NTEK provides comprehensive testing and certification services, applying AEC-Q100 automotive standards to control the safety and quality of automotive chips, supporting the growth of domestic automotive-grade chips and adding new momentum to the intelligent vehicle safety system.