The charged device model (CDM) is a distinct approach to simulating electrostatic discharge, differing from the human body model (HBM) and the machine model (MM). CDM focuses on the static charge that accumulates in electronic devices during production or logistics and the rapid discharge that occurs when the device touches ground or another conductive object. A CDM event is characterised by an extremely fast current rise, typically between 0.1 and 0.5 nanoseconds, with the whole discharge lasting about 6 to 8 nanoseconds, and its peak current can be several times higher than HBM under the same ESD conditions.

NTEK's automotive component laboratory provides professional ESD testing including CDM, to confirm the reliability and stability of electronic components when exposed to electrostatic discharge. Through our testing and assessment, customers gain a better understanding of the challenges their products may face in real applications and can take appropriate measures to protect their equipment from ESD damage.

The CDM test set-up

A CDM test set-up consists mainly of a field plate connected to a high voltage supply and a grounded pogo pin that can move between the pins of the device under test to simulate an actual ESD event. Figure 1 shows the practical test module and Figure 2 the equivalent circuit, where CDUT is the capacitance between the device and the field plate, CDG the capacitance between the device and the ground plane, and CFG the capacitance between the field plate and the ground plane.

Figure 1: practical test modules

Figure 2: equivalent circuit

(CDUT is the capacitance between the device and the field plate, CDG the capacitance between the device and the ground plane, and CFG the capacitance between the field plate and the ground plane.)

CDM test specifications

Before CDM testing was harmonised there were several reference standards, including JESD22-C101, ESDA S5.3.1, AEC-Q100-011 and EIAJ ED-4701/300-2, differing in calibration platforms, oscilloscope bandwidth and waveform verification parameters.

Advances in technology have improved transistor performance and increased demand for high-speed I/O. As ICs require faster I/O and integrate more functions in a single package, growing package size makes it harder to maintain the CDM discharge levels recommended in JEP157. Considering differences in charging resistance between testers, the ESD Association suggested in its 2020 roadmap that CDM target levels may need to be reassessed.

As electronic devices become more capable, the need for ESD protection grows. NTEK's automotive component laboratory provides professional ESD testing to help customers assess how their products perform in electrostatic discharge environments and offers tailored solutions based on the latest standards and recommendations.

With NTEK's testing services customers can understand their products' ESD performance more accurately and ensure reliability and stability in real use. Figures 3 and 4 show how CDM target levels have changed over the years and how the distribution of CDM ESD target levels is expected to shift.

Figure 3: CDM discharge target levels over the years

Figure 4: expected change in the distribution of CDM ESD target levels

Why the CDM requirements were adjusted

The reduction in CDM discharge capability required by JEP157 reflects several key factors.

1. The significant increase in pin count and package size. At a fixed pre-charge voltage, the CDM discharge capability is limited, especially by package size. More pins and larger packages mean the IC can store more charge, so peak current rises quickly during a CDM event. Under the same peak current limit, more pins and larger size therefore reduce CDM capability.

2. Advanced process technology lowering CDM capability. As process dimensions shrink, active devices become smaller and more fragile and metal interconnects become thinner and more resistive, reducing the robustness of ESD protection circuits. At the same current level, achieving CDM protection becomes harder.

3. Mixed-signal ICs combining high-speed digital, RF analogue and other performance-sensitive pins are becoming more common, imposing new requirements on ESD protection. In high frequency circuits, connecting protection devices directly to I/O pins can significantly degrade RF performance, so RF protection structures must be isolated from the core circuit, typically by inserting a shunt inductor or capacitor network between the protection device and the pin that presents near-zero impedance during low frequency ESD events and high impedance during normal high frequency operation. NTEK's automotive component testing laboratory is dedicated to providing professional ESD testing services, helping customers understand and assess how their products behave under electrostatic discharge and offering targeted solutions to ensure adequate reliability and stability.

About NTEK

NTEK Group, founded in 2009 and headquartered in Shenzhen, provides quality research services covering R&D verification, inspection and testing, failure analysis, simulation and market access for intelligent connected vehicles, electronic communications and new energy.

NTEK has extensive experience in automotive-grade electronic certification and has helped more than 100 companies pass AEC-Q series certification. Driven by the need of vehicle makers to localise automotive-grade components and supported by the domestic semiconductor industry, NTEK provides comprehensive testing and certification services, applying AEC-Q automotive standards to control the safety and quality of automotive components, supporting the growth of domestic automotive-grade components and adding new momentum to the intelligent vehicle safety system.